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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. d 05/09/2012 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is61c1024al is64c1024al 128k x 8 high-speed cmos static ram description the issi is61c1024al/is64c1024al is a very high- speed, low power, 131,072-word by 8-bit cmos static rams. they are fabricated using issi's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce1 is high or ce2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using cmos input levels. easy memory expansion is provided by using two chip enable inputs, ce1 and ce2. the active low write enable (we) controls both writing and reading of the memory. the is61c1024al/is64c1024al is available in 32-pin 300-mil soj, 32-pin 400-mil soj, 32-pin tsop (type i, 8x20), and 32-pin stsop (type i, 8 x 13.4) packages. functional block diagram a0-a16 ce1 oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 ce2 features ? high-speed access time: 12, 15 ns ? low active power: 160 mw (typical) ? low standby power: 1000 w (typical) cmos standby ? output enable (oe) and two chip enable (ce1 and ce2) inputs for ease in applications ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 5v (10%) power supply ? commercial, industrial, and automotive tempera- ture ranges available ? lead free available may 2012
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al truth table mode we ce1 ce2 oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc 1 , i cc 2 read h l h l d out i cc 1 , i cc 2 write l l h x d in i cc 1 , i cc 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 pin configuration 32-pin soj pin descriptions a0-a16 address inputs ce1 chip enable 1 input ce2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output v dd power gnd ground operating range (is64c1024al) range ambient temperature v dd automotive -40c to +125c 5v 10% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we ce2 a15 vdd nc a16 a14 a12 a7 a6 a5 a4 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 pin configuration 32-pin tsop (type 1) (t) and stsop (type 1) (h) operating range (is61c1024al) range ambient temperature v dd commercial 0c to +70c 5v 10% industrial -40c to +85c 5v 10%
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. d 05/09/2012 is61c1024al, is64c1024al absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to +7.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 5.0v. dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C4.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd com. C1 1 a ind. C2 2 auto. C5 5 i lo output leakage gnd v out v dd com. C1 1 a outputs disabled ind. C2 2 auto. C5 5 note: 1. v il = C3.0v for pulse width less than 10 ns.
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al is61c1024al/is64c1024al power supply characteristics (1) (over operating range) -12 ns -15 ns symbol parameter test conditions min. max. min. max. unit i cc 1 v dd operating v dd = v dd max ., ce1 = v il com. 35 ma supply current i out = 0 ma, f = 0 ind. 40 auto. 45 i cc 2 v dd dynamic operating v dd = v dd max ., ce1 = v il com. 45 ma supply current i out = 0 ma, f = f max ind. 50 auto. 55 typ. (2) 32 i sb 1 ttl standby current v dd = v dd max ., com. 1 ma (ttl inputs) v in = v ih or v il ind. 1.5 ce1 v ih , f = 0 or auto. 2 ce2 v il , f = 0 i sb 2 cmos standby v dd = v dd max ., com. 400 a current (cmos inputs) ce1 v dd C 0.2v, ind. 450 ce2 0.2v auto. 500 v in v dd C 0.2v, or typ. (2) 200 v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. d 05/09/2012 is61c1024al, is64c1024al read cycle switching characteristics (1) (over operating range) -12 -15 symbol parameter min. max. min. max. unit t rc read cycle time 12 15 ns t aa address access time 12 15 ns t oha output hold time 3 3 ns t ace 1 ce1 access time 12 15 ns t ace 2 ce2 access time 12 15 ns t doe oe access time 6 7 ns t lzoe (2) oe to low-z output 0 0 ns t hzoe (2) oe to high-z output 0 6 0 6 ns t lzce 1 (2) ce1 to low-z output 2 2 ns t lzce 2 (2) ce2 to low-z output 2 2 ns t hzce (2) ce1 or ce2 to high-z output 0 7 0 8 ns t pu (3) ce1 or ce2 to power-up 0 0 ns t pd (3) ce1 or ce2 to power-down 12 12 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads figure 1 figure 2 480 5 pf including jig and scope 255 output 5v 480 30 pf including jig and scope 255 output 5v
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace1 t ace2 t lzce1 t lzce2 t hzoe high-z data valid address oe ce1 ce2 d out t hzce1 t hzce2 ce2_rd2.eps notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce1 = v il , ce2 = v ih . 3. address is valid prior to or coincident with ce1 low and ce2 high transitions. read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. d 05/09/2012 is61c1024al, is64c1024al write cycle switching characteristics (1,2) (over operating range, standard and low power) -12 ns -15 ns symbol parameter min. max. min. max. unit t wc write cycle time 12 15 ns t sce 1 ce1 to write end 10 12 ns t sce 2 ce2 to write end 10 12 ns t aw address setup time to write end 10 12 ns t ha address hold from write end 0 0 ns t sa address setup time 0 0 ns t pwe (3) we pulse width 10 12 ns t sd data setup to write end 7 10 ns t hd data hold from write end 0 0 ns t hzwe (4) we low to high-z output 7 7 ns t lzwe (4) we high to low-z output 2 2 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with oe high. 4. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al write cycle no. 2 (oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce1 we d out d in oe data in valid t lzwe t sd high ce2 ce2_wr2.eps notes: 1. the internal write time is defned by the overlap of ce1 low, ce2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe = v ih . data undefined t wc valid address t sce1 t sce2 t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce1 ce2 we d out d in data in valid t lzwe t sd ce2_wr1.eps ac waveforms write cycle no. 1 (ce1 controlled, oe is high or low) (1 )
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. d 05/09/2012 is61c1024al, is64c1024al write cycle no. 3 (oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce1 we d out d in oe data in valid t lzwe t sd high ce2 ce2_wr3.eps
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al data retention switching characteristics symbol parameter test condition min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce1 v dd C 0.2v com. 200 400 a or ce2 0.2v ind. 450 v in v dd C 0.2v, or v in v ss + 0.2v auto. 500 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data retention waveform ( ce1 controlled) data retention waveform (ce2 controlled) vdd ce1 vdd - 0.2v t sdr t rdr v dr ce1 gnd 4.5v 2.2v data retention mode vdd ce2 0.2v t sdr t rdr v dr 0.4v ce2 gnd 4.5v 2.2v data retention mode
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. d 05/09/2012 is61c1024al, is64c1024al ordering information: is64c1024al automotive range: C40c to +125c speed (ns) order part no. packa ge 15 IS64C1024AL-15KA3 400-mil plastic soj is64c1024al-15ta3 tsop (type i) ordering information: is61c1024al commercial range: 0c to +70c speed (ns) order part no. package 12 is61c1024al-12t tsop (type i) ordering information: is61c1024al industrial range: C40c to +85c speed (ns) order part no. packag e 12 is61c1024al-12jli 300-mil plastic soj, lead-free is61c1024al-12ki 400-mil plastic soj is61c1024al-12kli 400-mil plastic soj, lead-free is61c1024al-12hi stsop (type i) is61c1024al-12hli stsop (type i), lead-free is61c1024al-12ti tsop (type i) is61c1024al-12tli tsop (type i), lead-free
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. d 05/09/2012 is61c1024al, is64c1024al note : 2. dimension d and e1 do not include mold protrusion . 4. formed leads shall be planar with respect to one another within 0.1mm 3. dimension b2 does not include dambar protrusion/intrusion. at the seating plane after final test. 1. controlling dimension : mm 5. reference document : jedec spec ms-027. seating plane 12/19/2007
14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. d 05/09/2012 is61c1024al, is64c1024al
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev. d 05/09/2012 is61c1024al, is64c1024al

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